vishay siliconix SI8805EDB new product document number: 67935 s12-1620-rev. b, 09-jul-12 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com p-channel 8 v (d-s) mosfet features ? trenchfet ? power mosfet ? ultra small 0.8 mm x 0.8 mm outline ? ultra thin 0.357 mm height ? typical esd protection 1500 v hbm ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? portable devices such as cell phones, smart phones, tablet pcs and media players - load switch for low voltage gate drive - load switch for 1.2 v power line notes: a. surface mounted on 1" x 1" fr4 board with full copper, t = 5 s. b. surface mounted on 1" x 1" fr4 board with minimum copper, t = 5 s. c. refer to ipc/jedec (j-std-020 ), no manual or hand soldering. d. maximum under steady state conditions is 185 c/w. e. maximum under steady state conditions is 330 c/w. product summary v ds (v) r ds(on) ( ? )i d (a) a q g (typ.) - 8 0.068 at v gs = - 4.5 v - 3.1 6.7 nc 0.088 at v gs = - 2.5 v - 2.7 0.155 at v gs = - 1.5 v - 2.1 0.290 at v gs = - 1.2 v - 0.5 micro foot device markin g : xxx = date/lot tracea b ility code ac orderin g information: si 88 05edb-t2-e1 (lead (p b )-free and halogen-free) b u mp side v ie w backside v ie w s d g s 1 2 4 3 ac xxx s d g p-channel mosfet absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 8 v gate-source voltage v gs 5 continuous drain current (t j = 150 c) t a = 25 c i d - 3.1 a a t a = 70 c - 2.5 a t a = 25 c - 2.2 b t a = 70 c - 1.8 b pulsed drain current i dm - 15 continuous source-drain diode current t a = 25 c i s - 0.7 a t a = 25 c - 0.4 b maximum power dissipation t a = 25 c p d 0.9 a w t a = 70 c 0.6 a t a = 25 c 0.5 b t a = 70 c 0.3 b operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) c 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, d t ? 5 s r thja 105 135 c/w maximum junction-to-ambient b, e 200 260
www.vishay.com 2 document number: 67935 s12-1620-rev. b, 09-jul-12 vishay siliconix SI8805EDB new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 % b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 8 v v ds temperature coefficient ? v ds /t j i d = - 250 a - 4 mv/c v gs(th) temperature coefficient ? v gs(th) /t j 2.1 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.35 - 0.7 v gate-source leakage i gss v ds = 0 v, v gs = 5 v 1.5 a zero gate voltage drain current i dss v ds = - 8 v, v gs = 0 v - 1 v ds = - 8 v, v gs = 0 v, t j = 55 c - 10 on-state drain current a i d(on) v ds ?? - 4 v, v gs = - 4.5 v - 5 a drain-source on-state resistance a r ds(on) v gs ?? - 4.5 v, i d = - 1.5 a 0.056 0.068 ? v gs ?? - 2.5 v, i d = - 1.5 a 0.070 0.088 v gs ?? - 1.5 v, i d = - 0.5 a 0.115 0.155 v gs ?? - 1.2 v, i d = - 0.3 a 0.190 0.290 forward transconductance a g fs v ds = - 4 v, i d = - 1.5 a 8s dynamic b total gate charge q g v ds = - 4 v, v gs = - 4.5 v, i d = - 1.5 a 6.7 10 nc gate-source charge q gs 0.7 gate-drain charge q gd 1.8 gate resistance r g f = 1 mhz 10 ? tu r n - o n d e l ay t i m e t d(on) v dd = - 4 v, r l = 2.7 ? i d ? - 1.5 a, v gen = - 4.5 v, r g = 1 ? 13 25 ns rise time t r 13 25 turn-off delay time t d(off) 25 50 fall time t f 17 35 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - 0.7 a pulse diode forward current i sm - 15 body diode voltage v sd i s = - 1.5 a, v gs ?? 0 v - 0.8 - 1.2 v body diode reverse recovery time t rr i f = - 1.5 a, di/dt = 100 a/s, t j = 25 c 35 70 ns body diode reverse recovery charge q rr 15 30 nc reverse recovery fall time t a 15 ns reverse recovery rise time t b 20
document number: 67935 s12-1620-rev. b, 09-jul-12 www.vishay.com 3 vishay siliconix SI8805EDB new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) gate current vs. gate-source voltage output characteristics on-resistance vs. drain current 0 0.5 1.0 1.5 2.0 2.5 3.0 0 3 6 9 12 15 i gss - gate current (ma) v gs - gate-source voltage (v) t j = 25 c 0 3 6 9 12 15 0 0.5 1 1.5 2 2.5 3 i d - drain current (a) v ds - drain-to-source voltage (v) v gs = 1.5 v v gs = 2 v v gs = 5 v thru 2.5 v v gs = 1 v 0 0.05 0.10 0.15 0.20 0.25 0.30 0 3 6 9 12 15 r ds(on) - on-resistance () i d - drain current (a) v gs = 1.8 v v gs = 1.2 v v gs = 1.5 v v gs = 2.5 v v gs = 4.5 v gate current vs. gate-source voltage transfer characteristics capacitance 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 0 3 6 9 12 15 i gss - gate current (a) v gs - gate-to-source voltage (v) t j = 150 c t j = 25 c 0 3 6 9 12 15 0 0.5 1 1.5 2 2.5 i d - drain current (a) v gs - gate-to-source voltage (v) t c = 25 c t c = 125 c t c = - 55 c 0 200 400 600 800 1000 0 2 4 6 8 c - capacitance (pf) v ds - drain-to-source voltage (v) c iss c oss c rss
www.vishay.com 4 document number: 67935 s12-1620-rev. b, 09-jul-12 vishay siliconix SI8805EDB new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) gate charge on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 1 2 3 4 5 0 2 4 6 8 v gs - gate-to-source voltage (v) q g - total gate charge (nc) v ds = 6.4 v v ds = 4 v v ds = 2 v i d = 1.5 a 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -50-250 255075100125150 r ds(on) - on-resistance (normalized) t j - junction temperature ( c) v gs = 2.5 v, i d = 1.5 a v gs = 1.8 v, 1.5 v, i d = 0.5 a v gs = 4.5 v, i d = 1.5 a v gs = 1.2 v, i d = 0.5 a 0 0.05 0.10 0.15 0.20 0.25 012345 r ds(on) - on-resistance () v gs - gate-to-source voltage (v) i d = 1.5 a; t j = 25 c i d = 0.3 a; t j = 25 c i d = 0.3 a; t j = 125 c i d = 1.5 a; t j = 125 c single pulse power (junction-to-ambient) source-drain diode forward voltage threshold voltage 0 2 4 6 8 10 12 14 0.001 0.01 0.1 1 10 100 1000 power (w) time (s) 0.1 1 10 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s - source current (a) v sd - source-to-drain voltage (v) t j = 150 c t j = 25 c 0.2 0.3 0.4 0.5 0.6 0.7 - 50 - 25 0 25 50 75 100 125 150 v gs(th) (v) t j -temperature ( c) i d = 250 a
document number: 67935 s12-1620-rev. b, 09-jul-12 www.vishay.com 5 vishay siliconix SI8805EDB new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) note: when mounted on 1" x 1" fr4 with full copper. * the power dissipation p d is based on t j(max) = 150 c, using junction-to-ambient thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the current rating, when this rating falls below the package limit. safe operating area, junction-to-ambient 0.01 0.1 1 10 100 0.1 1 10 100 i d - drain current (a) v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specied 10 s, 1s, 100ms 100 s limited by r ds(on) * 1 ms t a = 25 c bvdss limited 10 ms dc current derating* 0 1 2 3 0 25 50 75 100 125 150 i d - drain current (a) t a - ambient temperature ( c) power derating 0 0.2 0.4 0.6 0.8 25 50 75 100 125 150 power (w) t a - ambient temperature ( c)
www.vishay.com 6 document number: 67935 s12-1620-rev. b, 09-jul-12 vishay siliconix SI8805EDB new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient (on 1" x 1" fr4 board with maximum copper) 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 square wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01 t 1 t 2 notes: p dm 1. duty cycle, d = 2. per unit base = r thja = 185 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 single pulse 0.02 0.05 normalized thermal transient impedance, junction-to-ambient (on 1 x 1 fr4 board with minimum copper) 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 square wave pulse duration (s) normalized effective transient thermal impedance 1 0.1 0.01 t 1 t 2 notes: p dm 1. duty cycle, d = 2. per unit base = r thja = 330 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 single pulse 0.02 0.05
document number: 67935 s12-1620-rev. b, 09-jul-12 www.vishay.com 7 vishay siliconix SI8805EDB new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com package outline micro foot 0.8 mm x 0.8 mm: 4- bump (2 x 2, 0.4 mm pitch) notes (unless other wise specified): 1. all dimensions are in millimeters. 2. four (4) solder bumps are lead (pb)-f ree 95.5sn/3.5ag/0.7cu with diameter ? ? 0.165 mm to ? 0.185 mm. 3. backside surface is coated with a ti/ni/ag layer. 4. non-solder mask defined copper landing pad. 5. ? is location of pin 1. notes: a. use millimeters as the primary measurement. vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67935 . 4 x ? b d e s a a1 a2 s d e ac mark on backside of die s g d s xxx 3 4 1 2 e e 4 x ? 0.205 to 0.225 note 4 solder mask ~ ? 0.215 recommended land dim. millimeters a inches min. nom. max. min. nom. max. a 0.314 0.357 0.400 0.0124 0.0141 0.0157 a 1 0.127 0.157 0.187 0.0050 0.0062 0.0074 a 2 0.187 0.200 0.213 0.0074 0.0079 0.0084 b 0.165 0.175 0.185 0.0064 0.0068 0.0072 e 0.400 0.0157 s 0.180 0.200 0.220 0.0070 0.0078 0.0086 d 0.760 0.800 0.840 0.0299 0.0314 0.0330
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